The field of the present invention relates generally to a technique for cross-sectioning a crystalline material to provide a substantially atomically smooth surface. In particular, the field of the invention relates to preparation of semiconductor samples for Scanning Capacitance Microscopy (SCM), Scanning Tunneling Microscopy (STM) or other analysis techniques.
Many material analysis techniques require a sample to be cross-sectioned; that is, to be sliced in a direction substantially different than the planar surface. The semiconductor industry typically builds devices in a planar fashion, using thin-film techniques. As semiconductor devices shrink to sub-micron, and beyond sub 0.1 micron critical planar dimensions, analysis techniques for two-dimensional, cross-sectional images have become inadequate.
Much of the economic success of the semiconductor industry depends on the continued shrinking of devices, which makes circuits faster and more compact, while lowering the cost. Microprocessor and DRAM device dimensions have shrunk from critical dimensions of approximately 0.8 microns in 1990 to 0.18 microns in 1999.
It is currently possible to build devices for which there is no conventional way to obtain substantially accurate images of two dimensional dopant profiles. This impediment increases the difficulty in designing the next generation of smaller devices, since process or device improvements rely on knowledge of device geometries and electrical carrier distributions. Device design is typically an iterative process, where a prototype device is built, then tested and studied, and then the design is improved based on the knowledge gained from the first prototype. This design loop can occur several times before a production design is finished.
Additionally, Computer Aided Design (CAD) tools specific to the semiconductor industry rely on physical model development and calibration for predictive modeling of device designs before the actual devices are built. Therefore, part of the design loop involves CAD modeling, and those CAD models rely on accurate measurement of test devices.
A semiconductor electronic device operates by controlling the position and motion of charge carriers, typically electrons and holes. Dopants are introduced into a crystalline semiconductor material to locally supply carriers and to affect their behavior when the device is electrically operated. The designer of such devices must be able to create a process to place the dopants with spatial accuracy to optimize the device performance. As devices are shrunk to improve performance, dopant placement accuracy is vital to obtaining working devices and acceptable manufacturing yields.
Techniques for dopant profiling have been largely limited by two-dimensional spatial resolution. One dimensional techniques, such as Secondary Ion Mass Spectrometry (SIMS) have high spatial resolution in the depth dimension, but require areal dimensions larger than most semiconductor devices of interest. Cleave-and-Stain techniques provide two-dimensional images, but spatial resolution is far from adequate for modern device dimensions, and quantization of dopant concentration is severely limited. Conventional spreading resistance techniques are also limited in spatial resolution to dimensions much larger than most devices of interest today. Higher spatial resolution is needed for two dimensional, cross-sectional analysis techniques.
Scanning Capacitance Microscopy (SCM) is a fairly recent development for high spatial resolution images of electrical charge concentrations, which can represent the electrically active dopant concentration in the 1xc3x971015 to 5xc3x971021 per cubic cm range. Scanning Capacitance Microscopy apparatus is explained in U.S. Pat No. 5,065,103, which is incorporated herein by reference. This measurement technique uses an Atomic Force Microscope (AFM) apparatus, combined with a high-frequency capacitance sensor to extract local capacitance versus electrical potential (dC/dV) information. By scanning the AFM/SCM tip in two dimensions and processing dC/dV information, a spatial image of electrical charge concentrations is obtained. This technique can image the charge concentrations in two dimensions across the surface of a sample. No information of charge concentrations in the depth dimension is obtained with this method.
Researchers at Texas Instruments, University of Texas, Intel, University of Utah, Digital Instruments, The National Institute of Standards and others have used standard techniques for cleaving, and mechanically polishing the cleaved surface for two-dimensional imaging with one dimension being substantially orthogonal to the sample surface. H. Edwards, et. al., xe2x80x9cScanning Capacitance Spectroscopy: An analytical technique for pn-junction delineation in Si devices,xe2x80x9d Appl. Phys. Lett., 72, 698 (1998) and A. Erickson, et. al., xe2x80x9cQuantitative Scanning Capacitance Microscopy analysis of Two-Dimensional dopant concentrations at nanoscale dimensions,xe2x80x9d J Elec. Mat., 25, 301 (1996), U.S. Pat. No. 5,710,052, and U.S. Pat. No. 5,520,769 are incorporated herein by reference. The technique depends on conventional methods normally employed for Transmission Electron Microscopy (TEM) or Scanning Electron Microscopy (SEM) sample preparation. Mechanical polishing produces an undesirable atomically rough surface, which adds noise and degrades spatial resolution and quantization of charge. The cleaving process is very imprecise, therefore making the selection of a specific device for analysis difficult or impossible. Also, cleaving a wafer is destructive at the wafer level, severely restricting further processing of that wafer. Therefore, this technique is not practical as an in-situ process monitor since an entire wafer must be broken in order to analyze one process step.
Another example of a conventional attempt to solve the problem is a technique used by Charles Evans and Associates. K. J. Chao, et. al., xe2x80x9cApplications of AFM and SCM in Semiconductor Devices,xe2x80x9d Charles Evans and Associates Analytical Measurement Conference, Sunnyvale, Calif. 1999, incorporated herein by reference. They have developed a technique wherein a device is selected by photolithography. Plasma etching is then used to form an orthogonal surface which cross-sections the device of interest. The resulting structure resembles a pillar or thin vertical wall. The pillar or wall on which the cross-section exists is toppled so as to provide direct topside access to the orthogonal, cross-sectional surface. Mechanical polishing can be used on this newly formed surface if the toppled structure is mechanically secured to the wafer or another substrate. SCM is then used to image the charges in the cross-section of a device. A major disadvantage of this technique is that the cross-sectional surface is atomically rough since it was formed with plasma etching and possibly a subsequent mechanical polish. This has the undesirable effect of adding noise, degrading spatial resolution and quantization of charges. Another disadvantage of this approach is that each pillar containing a selected device for analysis must be manually toppled and secured to a substrate. Furthermore, an electrical ground must be provided for the small, toppled piece. Such intricate handling of small parts may introduce contamination and measurement errors, and requires additional preparation time by a skilled, dexterous person.
What is needed is a sample preparation technique to produce a substantially atomically smooth surface at an angle to the original sample surface, without breaking the entire wafer. It is also desirable to specifically select one or more devices for analysis, while leaving other devices on the wafer undisturbed. Furthermore, it would be desirable to select a specific portion of or exact location on specific devices. It would be advantageous to eliminate the handling or anchoring of small parts, and to be able to prepare many devices on a substrate for analysis at once, without operating on each device individually.
Once conventional SCM is used to measure capacitance versus electrical potential for each spatial scan point, this data must be converted to obtain corresponding electrical charge concentrations.
Conventional models have simplified the interaction of the SCM tip with the sample by using a one-dimensional, two-dimensional or quasi-three-dimensional structure. J. J. Kopanski, et. al., xe2x80x9cScanning Capacitance Microscopy Measurements and Modeling: Progress toward dopant profiling of silicon,xe2x80x9d J. Vac. Sci. Technol. B, 12, 242 (1996) and J. F. Marchiando, et. al., xe2x80x9cModel Database for Determining Dopant Profiles from Scanning Capacitance Microscopy Measurements,xe2x80x9d J. Vac. Sci. Technol. B, 16, 463 (1998), incorporated herein by reference.
Furthermore, conventional models have assumed that charge concentrations in the vicinity of each spatial sample point are uniform over the region of the sample influenced by the electrical potential of measurement tip. This assumption causes significant errors when the charge concentration gradient is large, such as gradients necessary in 0.18 micron and smaller transistors. One solution to this shortcoming, disclosed in U.S. Pat. No. 5,523,700 and incorporated herein by reference, uses a specialized feedback system to cause the scan to occur along iso-concentration paths, thus mapping contours of carrier concentration. This technique, however, requires specialized or modified equipment.
Another shortcoming of some conventional techniques is that they do not account for the actual radius of the SCM tip. Rather, these conventional models assume that the SCM tip is atomically sharp or a perfect point source for the applied potential.
Additionally, if the SCM tip is not oriented orthogonal to the surface, which may occur when measuring the aforementioned anisotropically etched surface, then the sidewall of the tip will electrically influence a region of the sample adjacent to the region directly under the tip. This angular tilt also causes a measurement error.
For accurate deconvolution of SCM data, what is needed is a technique for cataloging various physical scenarios with each corresponding SCM response, and a method for iterating on cataloged parameters to find the actual distribution of electrical charge from measured SCM data.
In order to overcome the above-discussed disadvantages of conventional sample cross-sectioning techniques, one aspect of the present invention utilizes the fact that certain etch chemistries are capable of anisotropically etching crystalline materials selectively, substantially stopping precisely on certain crystalline planes of atoms. A further aspect is that this etch process can be masked in selected regions so as to protect desired areas of a sample from the etch, while allowing other areas to be subjected to the etch. The etched region is bounded by the masked or lithographically defined region in the plane of the original sample surface, and is bounded in the depth direction by a crystallographic plane that serves as an etch stop. The angle of the newly-formed surface corresponding to the crystallographic plane relative to that of the original sample surface will depend on the specific crystal structure, and the specific etch chemistry. Additional polishing or smoothing of the surface can be accomplished using chemistries and techniques known to those skilled in the art to improve surface quality.
For example, if the substrate material is silicon with a starting surface having crystal orientation of  less than 100 greater than , and the etchant is Potassium Hydroxide (KOH) based, then the etch will substantially stop on the  less than 111 greater than  silicon crystal plane. This produces an angle between the original surface and the newly formed cross-sectional surface of 54.7 degrees, since the inverse-cosine of the normalized mathematical dot product between (1,0,0) and (1,1,1) is 54.7 degrees. In a preferred embodiment, Ammonium Fluoride chemistry is then used to improve surface quality by minimizing remaining asperities on the  less than 111 greater than  plane.
In accordance with another aspect of the present invention, specific devices or specific regions of specific devices can be selected using conventional photo- or electron-beam lithography. The selected devices and/or device regions are not necessarily selected at random. Additionally, many devices on a common substrate or wafer can be selected, patterned and etched at once, with a single lithographic mask or pattern using conventional methods known to those skilled in the art.
It will be appreciated that an aspect of the present invention utilizes anisotropic chemical etching and polishing to form a substantially atomically smooth surface apart from the starting sample surface and does not rely on mechanical polishing or the like. Therefore an aspect of the present invention provides previously unattainable true and clear images of electrical charge concentrations beneath the original sample surface in sub-micron devices. An aspect of the invention can be applied to other analysis techniques where a substantially atomically smooth cross-sectional surface is necessary or desirable.
A further aspect of the present invention is that the technique is non-destructive at the wafer or substrate level. A production wafer or substrate can incorporate many devices intended for testing and measurement purposes, not essential for final circuit operation. These test devices may be destroyed in the testing process using an aspect of the present invention, thereby serving as in situ monitors, or quality control devices. The results obtained from the testing of these devices may provide critical information needed to detect faults in manufacturing equipment, or errors made in prior processing steps. Nevertheless, the wafer on which these test devices reside can remain intact, and may be continued through completion of the manufacturing process after testing with an aspect of the present invention.
Because one aspect of the present invention allows testing at a specific location, automated testing is possible. In conventional methods, there are problems associated with either locating a specific device, or with tedious handling of small pieces separated from the original substrate. Another aspect of the present invention is that it allows economical device testing and analysis in a semiconductor fabrication facility using conventional laboratory equipment. Many points or devices on a substrate can be analyzed without adding significant cost, making high quality, across-the-wafer uniformity measurement inexpensive.
Another aspect of the present invention is that the angle between the original sample surface and the new, cross-sectional surface is precisely defined by the crystal geometry. This allows precise trigonometric scaling of at least one of the dimensional axes to provide an image that is representative of an orthogonal cross-section. Said angle need not be orthogonal to the original sample surface, which provides an effective magnification along at least one dimension, enhancing spatial resolution. Proper calibration of this dimension to a xe2x80x9cdepthxe2x80x9d scale is a simple trigonometric conversion.
The present invention is compatible with a variety of lithographic and masking techniques. For instance, optical, x-ray, e-beam, or direct-write AFM lithography can be used for patterning purposes in accordance with an aspect of the present invention. Furthermore, an aspect of the invention is compatible with a variety of measurement or analysis techniques such as Scanning Electron Microscopy (SEM), Scanning Tunneling Microscopy (STM), 4-point probe measurement, Auger Electron Spectroscopy (AES), Rutherford Backscattering (RBS), and various other methods where a smooth cross-section of a crystalline sample is useful or necessary.
A variety of scanning probe measurement techniques that can be applied to surfaces or near-surface regions are similarly applicable to an aspect of the present invention.
In order to overcome disadvantages of conventional SCM deconvolution techniques, an aspect of the present invention provides a database of structure parameters (tip tilt, oxide thickness, average concentration, concentration gradient, tip radius and tip DC bias) and corresponding theoretical dC/dV values. This database is then applied iteratively to determine accurate two-dimensional electrical charge concentrations from measured SCM data. Because there may exist multiple nodes in the database that match the measured data at a particular pixel or spatial scan point, data from neighboring pixels is incorporated in the selection of the appropriate matching node.
Said database is populated with theoretical data by simulating the electrical response from various tip/sample structures in a conventional three-dimensional electrical device simulator implementing relevant conventional electrostatic equations. xe2x80x9cDavinci User""s Manual,xe2x80x9d Technology Modeling Associates Inc. (1996) incorporated herein by reference.